moore’s law isn’t dead yet, we have mcm gpus incoming in 2 generations from now, with a data scheduler which aims to improve performance by 80-100% compared to monolithic GPUs, by intelligently organising information and sending information to specific cores to reduce processing latency and increase performance. It’s meant to be 80-100% more efficient than Lovelace (next gen nvidia architecture)
currently MCM architecture isn’t possible without such a scheduler, as sending information to different cores can increase latency which decreases end performance, in circumstances where information and a process in one core relies on and has to call on information and a process in the other core. That’s what the data scheduler is supposed to fix. Currently information is just thrown into the processor core in a random manner with no organisation.
Also next generation of nvidia GPUs will be a huge leap in performance and efficiency given they’re on TSMC 5nm, which could easily be a 80%-2x performance improvement over the current ampere gen.
Samsung 8nm is equiv. to 12nm TSMC, so it’s a huge node shrink.
Even though it’s just rumour that Lovelace is on Tsmc 5nm, it would have to be in order to compete with AMD since AMD is reportedly releasing a MCM architecture this year or next year for their next gen of GPUs. NVIDIA has to do a massive node shrink to TSMC 5nm to compete with AMD’s MCM GPU.
That probably means that Ampere will be available at RRP when Lovelace comes out, as Lovelace on TSMC is likely to be Turing prices or higher.
Lovelace will reportedly according to leaks have 80% more cuda cores than ampere, at 18k over amperes 10k cuda cores, which makes sense given how much of a node shrink it is they can fit almost double the amount of CUDA cores.
An nvidia equivalent infinity fabric may be coming too, which would increase performance and allow Nvidia to use lower bus size for the GPU and achieve the same performance.
GPUs which have up to a 512 bit bus could be released as well, which will have so much more bandwidth when combined with an infinity fabric type architecture
Then there’s GDDR6X/GDDR7, for AMD and nvidia
A refresh of the MCM hopper GPU could happen, which requires 3-4 power sockets to get that extra bit of performance out.
In addition there’s DDR5 ram around the corner which should be able to hit over 6000mhz-7000mhz, if not when it first comes out in the next couple years, faster ram means less frame drops and stuttering when information has to be called from ram and not L1, L2 or l3 cache
And there’s also PCI express 5.0 coming
for extra headset frames display port 2.0 can put out about 135 fps on Pimax’s large or normal fov.
display port 2.0 will probably get saturated by PCI express 5.0, so that means we’ll probably be seeing a display port 3.0 eventually with even more bandwidth.
I think the next few years of tech is looking bright, but availability is going to be zilch because of scalping bots instantly buying everything.
So here’s what I expect in advancements in the next few years
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(Next 2 yrs) Lovelace 5nm > 80% performance increase over ampere (with tsmc 12nm/samsung 8nm node shrink to TSMC 5nm)
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(Next 4 yrs) Hopper 4/3nm > 2-2.5x performance increase over Lovelace (with MCM data scheduler and node shrink from 5nm to 4-3nm)
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(Next 4-6 yrs) Infinity fabric in NVIDIA architecture 50%-2x increase over hopper
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(Next 6-8 yrs) 512 bit bus on NVIDIA architecture with infinity fabric> extra card bandwidth means extra performance - possibly a 60-70% increase over 300 bit bus architectures currently used.
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(Next 6-8 yrs) overclocked, overpowered 3nm MCM refreshes similar to ampere.
Of course those GPUs will probably have to be paired with PCIe 5.0 motherboards and DDR6 at 6/7000mhz in order to not be bottlenecked. PCIe 5.0 will probably become important when we have GPUs with 512 bit buses.
When we see software and games coded to take advantage of more cores and AMD architecture (when more cores become the lowest common denominator in hardware over the current 4-6 cores) then CPU bottlenecking shouldn’t be an issue in future games which can take advantage of more than 4 cores.
